The present invention relates generally to a semiconductor device, and more particularly to an electrostatic discharge protection device that protects an internal circuit from electrostatic discharge.
In general, a semiconductor device is provided with an electrostatic discharge (ESD) protection circuit as shown in FIGS. 1A to 3B. The ESD protection circuit is placed between an input/output pad and an internal circuit to prevent damage of the internal circuit due to excessive current having a large energy generated when static electricity charged in a human body or a machine is discharged to the internal circuit or the static electricity charged in the internal circuit flows to an external object.
Referring to FIGS. 1A and 1B, an ESD protection device having a grounded gate NMOS (GGNMOS) transistor protects an internal circuit 120 as a parasitic bipolar NPN transistor 130. The GGNMOS transistor N10 operates to discharge the static electricity generated between an input/output pad 101 and a ground pad 102.
More specifically, when static electricity is generated between the input/output pad 101 and the ground pad 102, a static electricity voltage due to the static electricity is applied between an N-type impurity region 106 as a collector and an N-type impurity region 108 as an emitter.
If the voltage exceeds the avalanche breakdown voltage of the PN junction formed with a P-well region 105 as a base and the N-type impurity region 106 as a collector, a plurality of electron-hole pairs is produced in a depletion region of the PN junction region and the electrons flow to the collector 106. The holes flow through the P-well region to a P-type impurity region 109 as a substrate contact of the transistor.
As the current due to the hole flows through a P-well resistor 131, a voltage drop is generated in the P-well region that causes a forward bias voltage to be applied across the PN junction between the N-type impurity region 108 as an emitter and the P-well region 105 as a base.
When the bias voltage becomes higher than the PN junction cut-in voltage of 0.7 V, the hole flows from the N-type impurity region 106 as a collector to the N-type impurity region 108 as an emitter and the electron flows in reverse, thereby triggering an operation of the NPN bipolar transistor 130.
However, since the avalanche breakdown voltage triggering the operation of the NPN bipolar transistor 130 in the GGNMOS transistor N10 is generally very high, i.e., over 6 to 7V, the ESD protection device provided with a GGNMOS transistor has a high trigger voltage which causes a problem.
Referring to FIGS. 2A and 2B, an ESD protection device having a gate coupled NMOS (GCNMOS) transistor detects alternating current (AC) components of static electricity using a RC circuit composed of a resistor 111 and a capacitor 110 and applies the components as a bias voltage to the gate 107.
Since the bias voltage is applied to the gate 107, the operation of the NPN bipolar transistor 130 is triggered at a voltage lower than the gate ground avalanche breakdown voltage, thereby lowering the trigger voltage as compared to the GGNMOS transistor.
Referring to FIGS. 3A and 3B, an ESD protection device having a substrate-triggered NMOS (STNMOS) transistor applies the AC components of static electricity to the P-well region 105 of the NPN bipolar transistor using the RC circuit and thus induces the current.
The base current triggers the operation of the NPN bipolar transistor 130 at a voltage lower than the gate ground avalanche breakdown voltage thereby lowering the trigger voltage as compared to the GGNMOS transistor.
However, the ESD protection device having either the GCNMOS transistor N20 or the STNMOS transistor N30 should include a RC circuit having a RC time constant of at least several ns for effective operation. A problem arises in that the area of the RC circuit is therefore increased.